I have one question concern with low level boot sequence.
- i.MX6DL @800MHz
- DDR3 x 4pcs. (64bit bus)
- SPI-NOR (u-boot and kernel)
- eMMC (RootFS)
When SPI-NOR boot is selected:
i.e. BOOT_MODE[1:0]=Internal Boot, BOOT_CFG1[7:4]=Serial ROM(SPI)
In this case, the system boot up sequence is as following :
- ROM code copy 4K byte data (include IVT and DCD table) from
SPI-NOR to OCRAM.
- Init the DDR base on the DCD table settings.
- Copy and Load the u-boot form SPI-NOR to DDR.
- Jump to DDR to executes the u-boot.
A piece of DDR was broken after ESD test, so DDR stress test became fail.
In other word, maybe above process 3, 4 (i.e.Copy and Load the u-boot / jump to DDR address) is not executed.