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Unable to configure MIPI/CSI2

Question asked by Ali Ismail on Aug 25, 2016
Latest reply on Aug 30, 2016 by Ali Ismail

So I am at a point where I have configured the mipi/cis2 interface. I am trying to configure VC2 to CSI0 in IPU2.


In imx6dql.dtsi the mipi/csi interface is defined.


mipi_csi: mipi_csi@021dc000 { /* MIPI-CSI */

                                compatible = "fsl,imx6q-mipi-csi2";

                                reg = <0x021dc000 0x4000>;

                                interrupts = <0 100 0x04>, <0 101 0x04>;

                                clocks = <&clks IMX6QDL_CLK_HSI_TX>,

                                         <&clks IMX6QDL_CLK_EMI_SEL>,

                                         <&clks IMX6QDL_CLK_VIDEO_27M>;

                                clock-names = "dphy_clk", "pixel_clk", "cfg_clk";

                                status = "disable";


In imx6dqscm_qwks_rev2.dts the mipi/csi is configured with IPU2(ipu_id = 1), CSI0(csi_id = 0), VC2 (v_channel=2) and 1 lane.


&mipi_csi {

        status = "okay";

        ipu_id = <1>;

        csi_id = <0>;

        v_channel = <2>;

        lanes = <1>;



IPU2 is also defined and configured already in imx6qdl.dtsi. My issue is that when I read memory address 0x021dc004 (MIPI_CSI_N_LANES) I get 0x00000003, which means there are 4 active data lanes. After looking at the rest of the registers, everything is in reset. Any hints on why everything is in reset and/or what I have to configure to get it out of reset?