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u-boot nand flash boot debug on t2080

Question asked by 小飞 杨 on Aug 26, 2016
Latest reply on Aug 31, 2016 by Adrian Stoica

Hi Experts:

 

Here is uboot booting related issue want to check with you.

 

Thanks a lot for your time!!

 

Background:

 

After DDR can be init successfully in init script(we use on-chip mem not DIMM, we add some GPIO operation before/after enbale DDR) , we go ahead to burn u-boot into Nand Flash and try to boot/debug u-boot from Nand Flash.

 


Question Description:
Under the description of T2080 datasheet and uboot source codes, after power-on reset, the processor starts at 0xfffffffc and the code is first executed in the last 4K page(0xfffff000-0xffffffff) in flash, but when we do some test, we found the real process looks like:
1) after power-on, looks the first 8K data will be copied to SRAM(IFC) by PBL, and then setting PLL etc. parameter based on RCW.
2) because we need to boot from NAND, so PBI will also be needed, PBL will run the PBI instruction to copy codes from SRAM(IFC) to SRAM(CPC)
3) for temporarily inited TLB only can access 4k bytes mem, so the codes will do some more init on LAW and TLB to get ability to access the rest of the memory space, the switch to ram to run the rest uboot codes

 

 

 

 

 

And under the guide of AN4876, we try to debug u-boot with the following steps:
1, burn u-boot-with-spl-pbl.bin(QorIQ-SDK-V2.0-20160527-yocto/build_t2080rdb-64b/tmp/work/t2080rdb_64b-fsl-linux/u-boot-qoriq/2016.01+fslgit-r0/git/T2080RDB_NAND_config) into flash

 

2, run u-boot.elf image after connect to target via USB TAP,  do reset let it go into resetvec, then do single step let it run into start.S one by one.

 

But on my side, after reset operation, it will stop at 0xfffffffc, if go forward(step out), it will hang in 0x700, can not go further any more.

 

It means there is no correct instruction in 0xfffffffc, checked in u-boot's link script(arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds), I found:
/*******************************************************/
SECTIONS
{
        . = 0xfff00000;
        .text : {
                *(.text*)
        }

.......
        .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
                KEEP(*(.resetvec))
        } = 0xffff
.......
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
#elif defined(CONFIG_FSL_ELBC)
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */

/*******************************************************/
There is no setting in 0xfffffffc.

 

And checked via readelf tool, I found the .text was put into 0x201000:
/**********************************************/
Section Headers:
  [Nr] Name
       Type            Addr     Off    Size   ES   Lk Inf Al
       Flags
  [ 0]
       NULL            00000000 000000 000000 00   0   0  0
       [00000000]:
  [ 1] .text
       PROGBITS        00201000 011000 067f1c 00   0   0 4096
       [00000006]: ALLOC, EXEC

/**********************************************/

 

 

 


So, currently, looks our u-boot still not get into start.S(arch/powerpc/cpu/mpc85xx/start.S), befor start.S, the running env should be setup by hardware setting(PBL,RCW), to boot from NAND, if we miss some important operation?

 

 

And do you have some comments about our understanding on the nand flash booting sequnce of t2080?

 

 

BTW, if DDR was inited in hardware init script(which was done by codewarrior), disable DDR init in u-boot will be okay when debugging?

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