First the back story:
I have a system of four K60 devices which are communicating over the CAN Bus. When the communication is occurring, the device and peripheral is clocked from the FLL driven by the RTC crystal.
From a fresh power up the system has no problems communicating. Every time the system comes up establishes CAN communications and then proceeds to do what it does. Once it starts doing what it does, it no longer talks over CAN for a while and switches it's clock to the PLL Driven by OSC0.
On a command it switches it's clock mode back to RTC driven FLL, and then resumes CAN communications.
After a variable number of clock source switches, CAN communications breaks down. There are many form and stuffing errors, as well as BIT1 errors.
I have been having great difficulty in tracking down the source of this issue. I've read vague rumblings about the FLL is not a good source for the CAN bus, but no firm documentation as to why.
Based on AN1798, the system should be able to tolerate at least a 1.4% to 1.5% clock error.
Any advice would be greatly appreciated.