P5020 srio port error

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

P5020 srio port error

868 Views
chaoxiang
Contributor I

hi all,

In my design, the srio port 2 ( lane A-D ) is connected to SRIO switch ( CPS-1848 ), and srio port 1 ( lane E-H )  does not connect to anything.

After initialization, I checked the P2ESCSR ( 0xfe0c0178 ) and P1ESCSR ( 0xfe0c0158 ).

P2ESCSR = 0x00000000

P1ESCSR = 0x00000001

From the P5020RM, bit 30 ( port ok ) and bit 31 ( port uninitialized ) should be mutually exclusive. But for port 2, they are both 0, which obviously contradict with the RM.

How did this happen?

best regards

Xiang Chao

Labels (1)
0 Kudos
2 Replies

524 Views
chaoxiang
Contributor I

hi all,

If I connect an FPGA to the srio port of p5020, its port_initialized flag will go active, but the link_initialized won't. There is no 8b/10b error for lane receiver. The SRIO_P1CCSR is d0600001, which means tx and rx are both enabled. When there is no FPGA connection, the SRIO_P1RSCSR is 00000001, so the tx and rx are not initialized. When I programmed the FPGA, the SRIO_P1RSCSR became 00000000, the tx and rx are initialized but the port ok flag did not go active.

It looks like the initialization process stuck at somewhere. Is there an register i need to set to kick start the srio device of P5020?

regards

Xiang Chao

0 Kudos

524 Views
ufedor
NXP Employee
NXP Employee

It will be convenient to investigate the issue as a Technical Case:

https://community.freescale.com/thread/381898

During creation of the Case please provide:

1) the processor connection schematics as searchable PDF

2) raw memory dump of the SRIO controller registers

3) binary image of the RCW being used

4) raw memory dump of the DCFG registers

0 Kudos