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KEA64 SPI Communication problem

Question asked by Ahn Joseph on Aug 22, 2016
Latest reply on Aug 25, 2016 by isaacavila

Enviroment : KEA64 EVB Kit --> Onsemi LED Driver with SPI Communication

Tool : KDS with P.E

Problem : The SS pin just one byte continue low state

                 Must be "SS Pin" to continue Turn Low (until complete 2byte)

                 I know that is Clock phase setting "Change on leading edge"

                Then I can chip selecting togging " No"

                Unfortunately, My target PCB can`t read

                when I setup [Clock phase setting : “Change on leading edge"]     

                So I tried Clock phase setting “Capture on Leading edge”

                then [chip selecting togging " Yes" ]

                And Other a GPIO port setting Output

               A GPIO port use to connecting target B.D SS port 

              The GPIO port sync to SPI communication time domain

              then I can transferdata.


   I want to setup Clock phase setting "Change on leading edge" & chip selecting togging " No"

   How can I setting above my desire ?


   Please look below my picture

   Blue line : GPIO out

   Line No2 : SS pin

   Line No3 : MISO

   Line No1: MOSI

   Line No0: CLK