Our customer have a question about i.MX6UL EIM access.
According to i.MX6 maximum EIM burst length and performance , EIM burst length is affected by the ARM instruction.
So they think that EIM execute single access (not burst access) even though it is synchronous mode if EIM memory region is set to uncacheable (L1/L2 cache) and if ARM issue single LOAD/STORE instruction to EIM memory region.
Is their understanding correct?
Do you know how memory attribute of EIM memory region set to uncacheable?