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Queries on iMX6 Solo processor : DDR3L Differentail clock,Video Decoder signals, PMIC F6 variant sequence

Question asked by ramesh t on Aug 22, 2016
Latest reply on Aug 24, 2016 by ramesh t
  • We are using 2-chip solution of 2G DDR3L SDRAM (128M x 16) memory. we are connecting DRAM_SDCLK_0 (P/N) from processorto first device (U2) of DRR3L CLK (P/N) and DRAM_SDCLK_1 (P/N) from processor to second device (U3) of DRR3L CLK (P/N).
    Is it correct ? (OR) Do we need to use any one DRAM_SDCLK from processor to DDR3L chips for 32 Bit configuration?
    Please see attachment Q1 snap-shot RED and Purple colour used to differentiate the Signals and connection in our schematic.

 

Q1.jpg

  • We are connecting Video Decoder Output signals to "EIM_A16 to EIM_A24" & "EIM_DA10 to EIM_DA12"  pins of SOC (i.MX6Solo). These SOC pins are used for Boot Configuration 3 & 4 and connected to ground through 10K ohm for proper Booting sequence, after booting these pins we used for CSI1 interface (ALT2).Is these 10K ohm pull down resistors will degrade our Video Decoder signal processing ?
    Please see attachment Q2 snap-shot RED & purple coloured.
    Q2.jpg

  • We used PMIC part number (MMPF0100F6AEP) based on its Default output of the switching regulator "SW3A & SW3B" is 1.35V which we were using for DDR3L . But this part number Power up sequence has slight difference from the earlier Part number (MMPF0100F0EP) which was used in SABRESD Flatform. VGEN6 (3.0V) O/P will be Sequence - 1 used for VDDHIGH_IN power pin of SOC & SW1AB (1.375 V), SW1C (1.375 V) O/P will be Sequence - 2 used for VDDCORE ,VDDSOC power pin of SOC. Is this sequence will cause any problem?

 

Thanks in Advance for your support.
Thanks & Regards,
Rameshkumar

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