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IMX6 Quad MIPI CSI 2 Multiple Device Interfacing

Question asked by Anuradha Ranasinghe on Aug 19, 2016
Latest reply on Aug 19, 2016 by igorpadykov

Hi All,

 

For a video processing application we are intending to use an HDMI and a CVBS analog camera inputs with IMX6 Quad processor. ADV7481 is an ideal solution to achieve both requirements through MIPI CSI 2 bus, however in ADV7481 HDMI and CVBS inputs are connected to two separated MIPI transmitters (4 lane for HDMI and a single lane for CVBS) and driven by two separated differential clock signals.

 

My question is, can we interface these two separated transmitter signals to single MIPI CSI 2 input of the IMX6 processor ? Let's say we configure the HDMI output to be 1 lane MIPI (out of 4), so we have clkp/clkn, d0p/d0n for HDMI and  by default clkp/clkn, d0p/d0n for CVBS output. Can these two differential clk lines be tied together ?

 

Thank You

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