AnsweredAssumed Answered

iMx6 linux clk driver question - clk-pfd.c

Question asked by Ken Lin on Aug 18, 2016
Latest reply on Aug 23, 2016 by igorpadykov

Hi,

 

Our platform defined PLL2 PFD2 as IPU1_DI0 clock source in kernel 4.7-stable for HDMI output.  When drm/hdmi driver is requesting for pixel clock 7875000 (in modeline 1024x768@75), it would fail to calculate the desired PFD2 source clock rate and fraction divider value. Is there anyone that could help explain the algorithm in clk_pfd_route_rate function in clk.pdf.c (especially for tmp=tmp*18 + rate/2)?

 

1. I added some debug messages in NXP clk-pdf.c driver (drivers/clk/imx/clk-pdf.c)

debug_message_clk_pdf_driver.png

 

2. The kernel messages show that the desired pixel clock for 1024x768@75 is 7875000 (in the test case - plug only the cable to Dell monitor after booting to linux console)

For some reason, it didn't proceed to run clk_pfd_set_rate, clk_pfd_recalc_rate routines@ in clk-pdf.c

 

drm_clk_debug_messages_log.png

 

3. HDMI clock source setting in kernel 4.7-stable device tree file

clk_source_setting_in_device_tree.png

 

4. The clock use case diagram

clk_use_case_diagram.png

Outcomes