zongmi tian

IMX51 Load Hive registry ,Can't into CE System sometimes.

Discussion created by zongmi tian on Aug 17, 2016

WINCE6。0增加了HIVE注册表之后。。重启十多次有可能就会出现一次进不去系统的情况。再重启又进去了。去掉HIVE注册表一切正常。。请问这种加了HIVE注册表就黑屏的情况是什么原因?如何解决?

不是硬件的问题。

硬件平台是IMX515 处理器,

希望能指点迷津万分感谢。我QQ39362580

WINCE6. 0 after adding the HIVE registry.. Restart more than and 10 times there may be a time to enter the system does not go to the CE System. Then restart and go in. Get rid of all the normal HIVE registry.. Does this with the HIVE registry on the black screen of what is the reason? How to solve?

Not a hardware problem.

Hardware platform is IMX515 processor,

Thank you very much hope to help.

 

 

USBHost : Detach Hub [address(1) / layer(0)]

INFO:OALLogSetZones: dpCurSettings.ulZoneMask: 0x1f

BSP Clock Configuration:

    CKIH        =   22579200 Hz

    PLL1        =  800000000 Hz

    PLL2        =  665000000 Hz

    PLL3        =  216000000 Hz

    LP_APM      =   24000000 Hz

    ARM         =  800000000 Hz

    AXI_A       =  166250000 Hz

    AXI_B       =  133000000 Hz

    EMI_SLOW    =  133000000 Hz

    AHB         =  133000000 Hz

    IPG         =   66500000 Hz

    PERCLK      =    8000000 Hz

    CKIL_SYNC   =      32768 Hz

    DDR         =  200000000 Hz

    ARM_AXI     =  166250000 Hz

    IPU_HSP     =  133000000 Hz

    VPU_AXI     =  166250000 Hz

    GPU         =  166250000 Hz

    GPU2D       =  166250000 Hz

    DEBUG_APB   =  166250000 Hz

    ENFC        =   26600000 Hz

    USBOH3      =   66500000 Hz

    ESDHC1      =   47500000 Hz

    ESDHC2      =   47500000 Hz

    ESDHC3      =   47500000 Hz

    ESDHC4      =   47500000 Hz

    UART        =   24000000 Hz

    SSI1        =    5644800 Hz

    SSI2        =    5644800 Hz

    SSI3        =    5644800 Hz

    SSI_EXT1    =   10285714 Hz

    SSI_EXT2    =   10285714 Hz

    USB_PHY     =   24000000 Hz

    TVE_216_54  =  216000000 Hz

    DI          =   27000000 Hz

    VPU_RCLK    =   24000000 Hz

    SPDIF0      =    1142857 Hz

    SPDIF1      =    1142857 Hz

    SLIMBUS     =   66500000 Hz

    SIM         =   66500000 Hz

    FIRI        =   24000000 Hz

    HSI2C       =   66500000 Hz

    SSI_LP_APM  =   22579200 Hz

    SPDIF_XTAL  =   24000000 Hz

    HSC1        =  216000000 Hz

    HSC2        =  216000000 Hz

    ESC         =   15428571 Hz

    CSI_MCLK1   =   24629629 Hz

    CSI_MCLK2   =   24629629 Hz

    ECSPI       =   66500000 Hz

    LPSR        =          0 Hz

    PGC         =   66500000 Hz

    OSC         =   24000000 Hz

    CKIH_CAMP1  =   22579200 Hz

    CKIH2_CAMP2 =          0 Hz

    CKIH2       =          0 Hz

    FPM         =   33554432 Hz

 

 

Microsoft Windows CE Bootloader Common Library Version 1.4 Built Feb  3 2016 00:02:27

INFO: BoardID = 0x0.

+OALPmicInit

CONTROLREG = 0x1f03011

CONFIGREG = 0x1000

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWrite

+OALPmicExchange

-OALPmicExchange

-OALPmicWrite

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

OALPmicInit:  silicon rev = 0x20

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicWriteMasked

+OALPmicExchange

-OALPmicExchange

+OALPmicExchange

-OALPmicExchange

-OALPmicWriteMasked

+OALPmicRead

+OALPmicExchange

-OALPmicExchange

-OALPmicRead

REV = 0x45d4

+OALPmicRead

+OALPmicExchange

-OALPmicExchange

-OALPmicRead

REG_SET0 = 0x20fd0

+OALPmicRead

+OALPmicExchange

-OALPmicExchange

-OALPmicRead

REG_MOD1 = 0x9

-OALPmicInit

Embo Windows CE Ethernet Bootloader 1.0 for MX51 EVK (Feb 15 2016 23:44:55)

INFO: SBMR = 0xE0600003.

INFO:  Bootloader launched from SD.

PWE_12V_EN EIM_A17 = 0!!!!!!!!!!!.

+ SDMMC_Init

SDHC_IsCardPresent OK.i=9

SetClockRate - Requested Rate: 150000 Hz, Setting clock rate to 148437 Hz

- SetClockRate

+ SDMMC_card_software_reset

- SDMMC_card_software_reset

+ SD_Init

+ SD_VoltageValidation

SDHCWaitEndCmdRespIntr Error Status: 10001

+ SDMMC_card_send_appcmd

SDHCWaitEndCmdRespIntr Error Status: 10001

- SDMMC_card_send_appcmd

SDMMC_card_send_appcmd() FAILURE!!! PassTime = 0.

- SD_VoltageValidation

+ MMC_Init

+ SDMMC_card_software_reset

- SDMMC_card_software_reset

+ MMC_VoltageValidation

MMC High Density card

- MMC_VoltageValidation

+ SDMMC_get_cid

- SDMMC_get_cid

+ SDMMC_send_rca

- SDMMC_send_rca

+ SDMMC_get_csd

- SDMMC_get_csd

SetClockRate - Requested Rate: 20000000 Hz, Setting clock rate to 15833333 Hz

- SetClockRate

+ SDMMC_set_data_transfer_mode

- SDMMC_set_data_transfer_mode

+ SDMMC_set_blocklen=0x00000200

- SDMMC_set_blocklen

+ SDMMC_get_ext_csd

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

- SDMMC_get_ext_csd

+ MMC_SetBusWidth

- MMC_SetBusWidth

MMC: Switched to 4 bit mode

- MMC_Init

INFO: Initialized MMC Card SDController.IsMMC = TRUE

- SDMMC_Init

WARNING: OEMPlatformInit: OK to initialize SDHC device.

INFO: Loading boot configuration from SDHC

SDImageCfg.dwSocId != 233 && SDImageCfg.dwSocId != 28.

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

INFO: Successfully loaded boot configuration from SDHC

INFO: OEMPlatformInit: OK.

System ready!

Preparing for download...

Embo Bootloader EbootDisplayInit()-->

PWE_12V_EN EIM_A17 = 0!!!!!!!!!!!.

 

 

Press [ENTER] to launch image stored in SD/MMC or [SPACE] to cancel.

 

 

Initiating image launch in 1 seconds.            0 seconds.

Launching flash image  ...

INFO: Using device name: 'MX5130874'

INFO: Reading NK image to SDHC (please wait)...

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

INFO:  dwActualLength = [0x1e907d4]

INFO: Copying NK image to RAM address 0xa0200000

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 1% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 2% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 3% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 4% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 5% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 6% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 7% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 8% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 9% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 10% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 12% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 13% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 14% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 15% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 17% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 18% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 19% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 22% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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INFO: Read is 26% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 27% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 28% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 31% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 32% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 35% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 36% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 37% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 40% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 44% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 49% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 50% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 53% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 54% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 55% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 58% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 59% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 62% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 63% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 66% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 67% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 68% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 70% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 71% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 72% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 75% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 76% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 77% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 80% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 81% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 84% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 85% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 86% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 89% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 90% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 91% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

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- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 93% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 94% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 95% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 96% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 97% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 98% complete+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

 

 

INFO: Read is 99% complete

INFO: Read is 100% complete

INFO: Copy of NK completed successfully

+ SDMMC_get_ext_csd

+ CheckDataStatus

- CheckDataStatus ESDHC_STATUS_PASS

- SDMMC_get_ext_csd

Download successful!  Jumping to image at 0x0 (physical 0x90200000)...

 

 

 

 

 

 

INFO:OALLogSetZones: dpCurSettings.ulZoneMask: 0x1f

BSP Clock Configuration:

    CKIH        =   22579200 Hz

    PLL1        =  800000000 Hz

    PLL2        =  665000000 Hz

    PLL3        =  216000000 Hz

    LP_APM      =   24000000 Hz

    ARM         =  800000000 Hz

    AXI_A       =  166250000 Hz

    AXI_B       =  133000000 Hz

    EMI_SLOW    =  133000000 Hz

    AHB         =  133000000 Hz

    IPG         =   66500000 Hz

    PERCLK      =    8000000 Hz

    CKIL_SYNC   =      32768 Hz

    DDR         =  200000000 Hz

    ARM_AXI     =  166250000 Hz

    IPU_HSP     =  133000000 Hz

    VPU_AXI     =  166250000 Hz

    GPU         =  166250000 Hz

    GPU2D       =  166250000 Hz

    DEBUG_APB   =  166250000 Hz

    ENFC        =   26600000 Hz

    USBOH3      =   66500000 Hz

    ESDHC1      =   47500000 Hz

    ESDHC2      =   47500000 Hz

    ESDHC3      =   47500000 Hz

    ESDHC4      =   47500000 Hz

    UART        =   24000000 Hz

    SSI1        =    5644800 Hz

    SSI2        =    5644800 Hz

    SSI3        =    5644800 Hz

    SSI_EXT1    =   10285714 Hz

    SSI_EXT2    =   10285714 Hz

    USB_PHY     =   24000000 Hz

    TVE_216_54  =  216000000 Hz

    DI          =   27000000 Hz

    VPU_RCLK    =   24000000 Hz

    SPDIF0      =    1142857 Hz

    SPDIF1      =    1142857 Hz

    SLIMBUS     =   66500000 Hz

    SIM         =   66500000 Hz

    FIRI        =   24000000 Hz

    HSI2C       =   66500000 Hz

    SSI_LP_APM  =   22579200 Hz

    SPDIF_XTAL  =   24000000 Hz

    HSC1        =  216000000 Hz

    HSC2        =  216000000 Hz

    ESC         =   15428571 Hz

    CSI_MCLK1   =   24629629 Hz

    CSI_MCLK2   =   24629629 Hz

    ECSPI       =   66500000 Hz

    LPSR        =          0 Hz

    PGC         =   66500000 Hz

    OSC         =   24000000 Hz

    CKIH_CAMP1  =   22579200 Hz

    CKIH2_CAMP2 =          0 Hz

    CKIH2       =          0 Hz

    FPM         =   33554432 Hz

Windows CE Kernel for ARM (Thumb Enabled) Built on Mar  8 2013 at 17:05:33

INFO:OALLogSetZones: dpCurSettinOALIoCtlHalInitRTC(2006/1/1 12:0:0.000)

CardBus.DLL DLL_PROCESS_ATTACH

BusEnum::BusEnum (ActivateRegPath=Drivers\Active\01)

ActivateChild: Template reg path is Drivers\BuiltIn\CSPDDK

ActivateChild: Template reg path is Drivers\BuiltIn\ECSPI1

ActivateChild: Template reg path is Drivers\BuiltIn\PMI

ActivateChild: Template reg path is Drivers\BuiltIn\ESDHC1

ActivateChild: Template reg path is Drivers\BuiltIn\SDBusDriver

BusEnum::ActivateChild load device driver at order 0

DeviceFolder::LoadDevice!Loading driver from device key Drivers\BuiltIn\CSPDDK

DeviceFolder::LoadDevice(Drivers\BuiltIn\CSPDDK) last 2 Ticks BusEnum::ActivateChild load device driver at order 1

DeviceFolder::LoadDevice!Loading driver from device key Drivers\BuiltIn\ECSPI1

DeviceFolder::LoadDevice(Drivers\BuiltIn\ECSPI1) last 2 Ticks BusEnum::ActivateChild load device driver at order 2

DeviceFolder::LoadDevice!Loading driver from device key Drivers\BuiltIn\PMI

DeviceFolder::LoadDevice(Drivers\BuiltIn\PMI) last 6 Ticks BusEnum::ActivateChild load device driver at order 21

DeviceFolder::LoadDevice!Loading driver from device key Drivers\BuiltIn\SDBusDriver

SDBusDriver: PROCESS_ATTACH

SDBusDriver: +SDC_Init

SDBusDriver: Bus Driver instance created : 0xD0048AC0 ! -SDC_Init

DeviceFolder::LoadDevice(Drivers\BuiltIn\SDBusDriver) last 10 Ticks BusEnum::ActivateChild load device driver at order 33

DeviceFolder::LoadDevice!Loading driver from device key Drivers\BuiltIn\ESDHC1

SDHCDGetHCFunctions: +Init

SDHCDGetHCFunctions: -Init

SDHC +Init

SDHC Active RegPath: Drivers\Active\06

+CESDHCBase::Init: Active RegPath: Drivers\Active\06

SlotpOptionHandler: Caps = 0x13c, HSS = 0x1

SDHCInitialize++

CESDHCBase::Start: PROCTL set value = 7000021

CESDHCBase32BitADMA2:Create DMA Object for ADMA2

+OALIoctlHalGetCacheInfo(...)

-OALIoctlHalGetCacheInfo(rc = 1)

SDHCInitialize--

-CESDHCBase::Init

SDHC -Init

DeviceFolder::LoadDevice(Drivers\BuiltIn\ESDHC1) last 37 Ticks

 

stop in here.

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