1) How do customer's control GPIO ISR affinity in SDK 2.0? At this point we don’t know how to assign these interrupts to any core other than Core#0.
2) It looks like the existing GPIO driver does not support assigning interrupts to any other core than CPU0, is this correct?
3) If so, why are GPIO interrupts assigned only to Core#0?
4) There are virtual GPIO interrpts and GPIO hardware interrupts, can either or both interrupts be assigned to a specific core other than Core#0?
Creating the GPIO interrupt on 1043:
root@ls1043ardb:~# echo 498 > /sys/class/gpio/export
root@ls1043ardb:~# echo falling > /sys/class/gpio/gpio498/edge
root@ls1043ardb:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
[....]
66: 0 0 0 0 GIC 106
Level 1740000.jr
67: 0 0 0 0 mpc8xxx-gpio 18
Edge gpiolib
IPI0: 3226 4833 4237 4170 Recheduling interrupts
IPI1: 17 21 19 23 Function call interrupts
Setting GPIO affinity doesn’t work:
root@ls1043ardb:~# echo 1 > /proc/irq/67/smp_affinity_list
-sh: echo: write error: Input/output error
Setting eMMC interrupt affinity works just fine:
root@ls1043ardb:~# echo 1 > /proc/irq/12/smp_affinity_list
root@ls1043ardb:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
[....]
1: 0 0 0 0 GIC 29
Edge arch_timer
2: 35475 39336 28975 38803 GIC 30
Edge arch_timer
11 9 0 0 0 GIC 75 Level fsl-ifc
12: 3370 14 0 0 GIC 94 Level mmc0
[...]
