Skew for the level translator 74AVC32T245EC?

[khadershareef]

Hi,

We are using the voltage level translator 74AVC32T245EC for 1.8V to 3.3V level translation (A -> B). There are 4x 8-bit bus namely 1An, 1Bn, 1Cn and 1Dn. And also I understand that the propagation delay provided (For ex:) is 0.5ns (min) to 3.3ns (max) for the case of Vcc(A) = 1.8V, Vcc(B) = 3.3V.

The bus frequency is 150 MHz (max) and to analyze the timings, we need to know the maximum possible skew for signals as below:

1. Within a bus (1A1 to 1A2 or 2A1 to 2A7)

2. Across a bus (1An to 2An or 3An or 4An)

I was not able to locate this information in the 74AVC32T245EC datasheet and hence your quick support would be helpful.

Regards,

Shareef

[Bulat]

NXP does not specify skew between individual buffers. So you should assume that the skew can be as much as the delta between the min and max propagation delay values.

Actually all buffers within a chip have very similar dynamic characteristics, however again, NXP does not specify that.

Regards,

Bulat

[khadershareef]

Bulat,

Thanks. I was a bit surprised with the response, since the device claims 380 Mbit/s data transfer through it from 1.8V to 3.3V level translation and if I had to consider the propagation delay values for my skew then it will be very difficult to meet timings at my destination receiver chip.

Your second line on "Actually all buffers within a chip have very similar dynamic characteristics" sounds realistic to me and the propagation delay values min/max might consider PVT characterization of the device. However I was expecting an approximate value of skew which NXP can share based on the actual device char. data. Please respond.

Regards,

Shareef

[Bulat]

Of course my first statement (..delta between the min and max..) was about potential skew in temperature range, not at the same time / same temperature. I think everyone wants his/her design be functional not at 25C degree only.

And I have to repeat, we do not specify the skew, sorry. This kind of specs is typically a must for clock drivers with multiple fan-out outputs, but not for bus buffers.

Regards,

Bulat