Some questions on the External Memory Controller (EMC) on the LPC43xx:
Reference, per App Note 11508:
- If I understand this correctly the benefit of using SFSCLK0/2 set to function 5 along with connecting CLK1 to the SDRAM rather than
CLK0, is to reduce the round trip delay of the CLKx signals (out to RAM and back) used for the “byte lane feedback clocks”?
See section 126.96.36.199 Best performance using a single SDRAM device and CCLK Div2:
- So does this setup work equally as well for CCLK not divided by 2?
- Using CLK2 and CLK0 unconnected (in mode 5) so that theyjust drive internal EMC_FBCLK23 and EMC_FBCLK01 respectively, is better or
worse than using each CLKx to drive EMC_FBCLKx directly (one CLK out to SDRAM)?