I am trying to reuse the DDR3 routing of SABRE SDP (LAY-27392_C.brd). While reviewing the routing of DDR3, I found the violation of the recommended routing rule in Hardware Development Guide document (IMX6DQ6SDLHDG).
For example, IMX6DQ6SDLHDG recommended that the address and control signal to match within +/- 25mils, but as a result of measuring the length between i.mx6 and DDR, there is maximum difference of 170 mils as below.
|Tolerance between signals (mils)||169.67||166.541||171.626||169.832|
When I reuse the DDR routing of LAY-27392_C.brd intactly, I am very apprehensive about the violation of the routing rule as above.
Is the skew possible to optimize using DDR3 calibration tool?
Can you give any advise?