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I.MX6Q SABRE SDP DDR3 routing rules violation.

Question asked by Seung-Gon Hong on Aug 9, 2016
Latest reply on Aug 9, 2016 by Yuri Muhin

I am trying to reuse the DDR3 routing of SABRE SDP (LAY-27392_C.brd). While reviewing the routing of DDR3, I found the violation of the recommended routing rule in Hardware Development Guide document (IMX6DQ6SDLHDG).

For example, IMX6DQ6SDLHDG recommended that the address and control signal to match within +/- 25mils, but as a result of measuring the length between i.mx6 and DDR, there is maximum difference of 170 mils as below.

  

Signal NameU1-U2U1-U3U1-U4U1-U5
DRAM_A7 (mils)1842.0961840.8921840.5691840.7
DRAM_A10 (mils)1672.4261674.3511668.9431670.868
Tolerance between signals (mils)169.67166.541171.626169.832

 

When I reuse the DDR routing of LAY-27392_C.brd intactly, I am very apprehensive about the violation of the routing rule as above.

Is the skew possible to optimize using DDR3 calibration tool?

Can you give any advise?

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