I.MX6Q SABRE SDP DDR3 routing rules violation.

[technect]

I am trying to reuse the DDR3 routing of SABRE SDP (LAY-27392_C.brd). While reviewing the routing of DDR3, I found the violation of the recommended routing rule in Hardware Development Guide document (IMX6DQ6SDLHDG).

For example, IMX6DQ6SDLHDG recommended that the address and control signal to match within +/- 25mils, but as a result of measuring the length between i.mx6 and DDR, there is maximum difference of 170 mils as below.

Signal Name	U1-U2	U1-U3	U1-U4	U1-U5
DRAM_A7 (mils)	1842.096	1840.892	1840.569	1840.7
DRAM_A10 (mils)	1672.426	1674.351	1668.943	1670.868
Tolerance between signals (mils)	169.67	166.541	171.626	169.832

When I reuse the DDR routing of LAY-27392_C.brd intactly, I am very apprehensive about the violation of the routing rule as above.

Is the skew possible to optimize using DDR3 calibration tool?

Can you give any advise?

[Yuri]

Hello,

  Please refer to the following iMX6 DDR3 Routing on Sabre Dual Lite board

Have a great day,
Yuri

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