I am using DMA to transfer data via the eLBC on P1025. I want to look at the time difference between setting CS (start transfer) and CB (transfer in progress) being set. Is there any information regarding this timing? I am particularly concerned with the nominal time and maximum boundary.
Note: we have a custom DMA driver (within an RTOS) that checks for CB=1 after CS=1; to verify job submission. Sometimes the driver misses the CB=1 event and assumes an error. If we interrupt lock the code between CS=1 and CB=1 it's ok, but I want to minimise the potential interrupt lock period.