When executing from internal flash Block 1 and writing 1KiB sectors of Block 0 flash for application update using the IFsh1 PEx-generated driver IFsh1_SetBlockFlash() function, data isn't always written, or ERR_SPEED is returned.
Toolset: CodeWarrior 10.6
Processor Expert version: 10.6.3.RT6_b1446-0504
MQX version: 4.1
Binary image being written - size: ~479KiB
Start address: 0x00008000
Component Configuration in Processor Expert:
Write method: Destructive write
Interrupt Service: disabled
Wait in RAM: yes
Virtual Page: disabled
Initialization: Events enabled in init: yes; Wait enabled in init: yes
CPU clock/speed selection: High speed mode - enabled, others disabled
All sector writes are IntFlashLdd1_ERASABLE_UNIT_SIZE using IFsh1_SetBlockFlash(), except for the last one (remainder).
Application execution from image starting address: 0x00080000 (Block 1)
Tasks: 6 ready or blocked
From looking at the code for IntFlashLdd1.c, I see that SafeRoutineCaller() calls _int_disable() before calling the SafeRoutine and calling _int_enable() after. Thus there should not be a context switch during the actual write operation.
When I added routines to verify each sector immediately after writing them to flash, many bytes remained in erased state (0xFF). When I added a routine to calculate the MD5 hash/sum of the image just written using the mmCAU MQX library, I end up with bytes in the last sector remaining in the erased state. Obviously, the md5sum will not match the expected.
When not attempting to verify or calculate MD5 sum, I occasionally get a return code from IFsh1_SetBlockFlash() of 0x01. From the header of the function, ERR_SPEED is the return value of 0x01. (The error description makes no sense in the source header, BTW, i.e. not applicable). Tracing the source of the bit analytically, it would have to be FTFE_FSTAT.MGSTAT0. The description in K70P256M150SF3RM reference manual section 30.34.1, "The MGSTAT0 status flag is set if an error is detected during execution of an FTFE command or during the flash reset sequence."
None of the other error bits are set.