Query regarding external oscillator frequency selection for PLL Configuration based on S12ZVC Evaluation board.

Question asked by Bhushan Patil on Aug 5, 2016

Hi,

I am using S1912ZVCA19F0WKH (magni v 192kB) controller.

In the VLG_MC9S12ZVC project demo code which we got along with Evaluation board.

The PLL configuration is as below.

//inits the pll

void PLL_init() {

CPMUCLKS_PLLSEL = 1; //FBUS = FPLL/2.   FBUS = 32MHz,

CPMUREFDIV_REFFRQ = 1; //Reference clock between 2MHZ and 6MHZ.

CPMUREFDIV_REFDIV = 0x1; //FREF=8/(1+1) = 4MHZ

CPMUSYNR_VCOFRQ = 0x1; //FVCO is between 48MHZ and 80MHZ

CPMUSYNR_SYNDIV = 0x7; //FVCO = 2xFREFx(SYNDIV+1)   =   FVCO = 2x4x(7+1) = 64MHZ

CPMUPOSTDIV_POSTDIV = 0x0; //FPLL = FVCO/(POSTDIV+1).  FPLL = 64MHZ/(0+1)    FPLL = 64MHz

CPMUOSC_OSCE = 1; //External oscillator enable. 8MHZ. FREF=FOSC/(REFDIV+1)

while(!CPMUIFLG_LOCK){} // Wait for LOCK.

CPMUIFLG = 0xFF; // clear CMPMU int flags - not needed but good practice

}

But the external oscillator used in evaluation board is of 4MHz.

I would like to know why external oscillator frequency(fosc) is considered as 8Mhz in the configuration for calculating Fref.

FREF=FOSC/(REFDIV+1): FREF=8/(1+1) = 4MHZ.

If I consider fosc = 4Mhz for calculating reference frequency based on formula I need to set REFDIV = 0 ; to achieve 4Mhz of reference frequency.

If I use REFDIV = 0 ,  PLL lock will not happen.

Please let me know on what basis fosc is considered as 8Mhz.

Regards,

Bhushan