I am using S12ZVC Evaluation Board.(S912ZVCA19F0WKH [magni v 192kB])
It has been observed that the port pins PS0 and PJ0 when configured as GPIO(Outputs) and forced to logic level HIGH
by writing to the respective Data Direction Register(DDRx) and Port Data Register(PTx) does not reflect into HIGH level on board.
Instead of both the pins (PS0 and PJ0) driven to 5 Volts the behavior observed was as mentioned below:
Physical Voltage on PS0 Pin - 3 Volts
Physical Voltage on PJ0 Pin - 0.1 Volts(Approx)
Guidance on the deviation of the results will be helpful !
Thanks & Regards,