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T2080 DDR3 data rate to DDRCLK ratio

Question asked by xiaopeng ma on Aug 6, 2016
Latest reply on Aug 6, 2016 by ufedor

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In my design,DDRCLK = 133.3MHz.

I want to set that DDR Bus CLK = 667MHz,DDR data rate = 1333MHz.

So I should choose MEM_PLL_RAT = 00_0101?

But when I config rcw through QCVS,I select DDR data rate/DDRCLK = 10:1,

then DDR data rate is displayed as 1.33GT/s,

the MEM_PLL_RAT = 00_1010.

Which one is correct?

Thanks.

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