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Do all the Freescale/NXP ARM Cores permit write-thru cache policy? From ARM documents A-7 seems to.

Question asked by Russ Massey on Aug 4, 2016
Latest reply on Aug 10, 2016 by Pavel Chubakov

According to ARM, A-7 permits write-thru cache policy. Does LS1022A implement this? What about other Freescale/NXP ARM cores?

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