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关于K64中的SPI的非FIFO的使用(disable FIFO of SPI slave)

Question asked by yuanhan chen on Aug 4, 2016
Latest reply on Aug 8, 2016 by yuanhan chen

我在使用非FIFO的时候,遇到了这样一个问题:就是在仿真的时候,从机接收中断函数打断点,查看在read POPR寄存器后,RX FIFO就会载入下一个数据,而非是空的,在测试之后我有一个猜想:因为在使用单步执行时,从执行read POPR命令后到下一句之间的时间被拉长了,长到这个时间足够主机传来的数据被RX FIFO接收(夸张的说,如果时钟够快,在正常接收到数据之前的时间段上打断点,在执行到这个断点时,查看RX FIFO都会显示有下一帧的数据,因为在遇到断点停止的一刹那,就已经有足够的时间使得数据被接收到) ,所以在下一句的时候,寄存器会出现的现象是:RX FIFO并没有空,而是保存了下一帧的数据。




I was in the use of non-FIFO, encountered such a problem: the simulation time, receives from the interrupt function break point, after viewing read POPR register, RX FIFO will load the next data, not empty and after the test I have a guess: because the use of single-step, from the command to execute read POPR a time between being stretched under a long enough time to the data from the host is received RX FIFO (exaggeration to say that, if the clock is fast enough, in normal reception of the break point in time before the data segment in the implementation of the breakpoint to view the RX FIFO data will show the next frame, since the breakpoint is encountered stop the moment, we have enough time so that the data is received), so the next one when the register phenomenon occurs is: RX FIFO did not have time, but save the data for the next frame.

We can discuss the next is not the reason.