MMA8652 TAP Polarity

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MMA8652 TAP Polarity

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edmon
Contributor II

Hi everyone, I have been working with MMA8652 for quite sometime now. I need to determine the tap direction specially in the z-axis. I have been following this example here: MMA8451Q -Single Tap Detection Bare metal example project. When I tap on top of the board (z-axis), it will always give me a value of C0 or C4 at Reg( 0x22). It will also gave me the same value when I tap at the bottom part. Thus, it is confusing if the hit comes from the top or bottom.

 

Since the example and application notes is using MMA8451. I compared it to MMA8652. I noticed that in MMA8451, REG0x2A has LNOISE bit (bit 2) but it is reserved in MMA8652. Will this make a difference?

 

In the attached is our initialization set-up and tap function.I hope to hear a feedback on how to deal with this. Thanks!

 

Regards,

Edmon

Original Attachment has been moved to: MMA8652_Init-and-TAP-Function.txt.zip

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reyes
NXP TechSupport
NXP TechSupport

Hi Edmon,

LNOISE bit is not necessarily used in directional Tap applications, so this should not be a problem for the MMA8652 to detect the directional tap.

Writing an algorithm to detect directional tap is slightly different from writing an algorithm to detect single tab, the biggest challenge is that all the pulses have a positive and a negative signal as can be seen in Figure 2 of the application note AN4072​, so you need to determinate which one is greater to determinate the direction.

Now, since you are getting C0 or C4 at register 0x22, then this makes me think that your code is working well, but you only need to adjust some settings like the timing and thresholds, find below some hints that may help you to solve the tap direction:

  1. Configure the accelerometer to be in 800 Hz 8g Mode
  2. I recommend you to test with the z-axis single tap threshold to 3.19g
  3. Set the Time Limit to 50 ms for the pulse and set the latency to 500 ms
  4. Look at the Max and Min values of each axis whose flag was detected in the pulse source register.
  5. Determine the direction: If the first peak is greater in absolute value than the second peak, it is a positive tap, otherwise it is a negative tap.

I hoe this can be useful.

Have a great day,
Jose

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ipx002
Contributor I

I read the datasheet , PLUSE_LTCY max is 318 ms. Can you set the latency to 500ms ?

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reyes
NXP TechSupport
NXP TechSupport

Hi JunLin Wu,

Yes, it is possible, but the configuration would depend on the ODR and Power Mode configuration you are using. The formula to calculate the needed configuration for the needed Pulse Latency is:

Pulse Latency (ms) / Time Step (ms) = PULSE_LTCY value

So we need to calculate the Time Step.

I will give an example below to try to make things more clear:

For this example I would say that my goal is to have 200ms of pulse latency, I’m using the following configuration:

ODR = 200Hz

Power Mode: Low Power (LP) Mode

Low Pass Filter = LPF is not enabled.

Now take a look at the following image (Table 83 and Table 84 of the MMA8652 datasheet):

pastedImage_0.png

Based in my configuration I get that the Time Step is 5ms, so:

Pulse Latency (ms) / Time Step (ms) = PULSE_LTCY value

200ms / 5ms = 40 counts (0x28)

Code Example: IIC_RegWrite(0x27, 0x28).

Making another example, but for a desired Pulse Latency of 500ms, I will assume the following configuration: ODR = 100Hz, Power Mode = Normal mode, and Low Pass Filter = Pulse_LPF_EN = 1, then I would use Table 83 and I would get that the Time Step for this configuration is 20ms, therefore:

Pulse Latency (ms) / Time Step (ms) = PULSE_LTCY value

500ms / 20ms = 25 counts (0x19)

Code Example: IIC_RegWrite(0x27, 0x19).

I hope this information can be useful.


Have a great day,
Jose

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ipx002
Contributor I

Thank you for your reply !

This is caused by my carelessness.

Thanks again !

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