About ERR004536 in IMX6DQCE Rev.6.1.

[keitanagashima]

Dear All,

Hello. I have questions about the ERR004536 in IMX6DQCE Rev.6.1.

[Q1]

This errata seems to influence by using ADMA2.

Is jb4.2.2_1.1.0 using ADMA2?

[Q2]

The below description is described.

"the incorrect block count will be loaded by the DMA engine."

i.e. it isn't possible to read data correctly, is it?

[Q3]

How should one confirm this problem?

My customer wants to confirm whether or not correspond to this errata on their system.

Best Regards,

Keita

[keitanagashima]

Hi All,

Do you have any update?

Best Regards,

Keita

[gusarambula]

Hello Keita Nagashima,

I’m investigating. I’ll let you know as soon as I find something regarding this erratum.

Regards,

[keitanagashima]

Hi gusarambula,

Do you have any update?

Please answer to me asap.

Best Regards,
Keita

[gusarambula]

Hello Keita Nagashima,

I’m very sorry for the delay. Please find the answers below:

[Q1]This errata seems to influence by using ADMA2. Is jb4.2.2_1.1.0 using ADMA2?

Yes, it is.

[Q2]The below description is described. "the incorrect block count will be loaded by the DMA engine."i.e. it isn't possible to read data correctly, is it?

Yes, some read data can be incorrect if the block counter is wrong.

[Q3]How should one confirm this problem? My customer wants to confirm whether or not correspond to this errata on their system.

Although not a very common or easily reproducible problem does depend on the use case and OS. The customer may encounter a SDIO timeout while performing a transfer. Switching to SDMA mode for blocksize < 512 bytes resolves the issue although does have some performance impact

Regards,

[keitanagashima]

Hello gusarambula,

Thank you for your reply.

My customer product status is already "Mass Production".

So, they must clarify this detail impact on their product.

[Q1]

Please tell me the frequency of reproducibility about this issue.

If this issue depends on the use case, please tell me the frequency of reproducibility with worst case.

[Q2]

How did you find this problem? (Simulation? or Actually occurring problem?)

[Q3]

There is description of "total latency of these AHB SINGLE bus accesses" in Chip errata.

How should we check this total latency?

Best Regards,

Keita

[gusarambula · Accepted solution]

Helo Keita Nagashima,

Please find the answers below:

[Q1] Please tell me the frequency of reproducibility about this issue.

If this issue depends on the use case, please tell me the frequency of reproducibility with worst case.

This is not a very easy issue to reproduce. A customer did observe an SDIO timeout while performing a WiFi transfer.

[Q2] How did you find this problem? (Simulation? or Actually occurring problem?)

We have had a few customers report this issue.

They were able to reproduce this issue on standalone simulation with very low AHB bus freq(a few Mhz).

 [Q3] There is description of "total latency of these AHB SINGLE bus accesses" in Chip errata.

How should we check this total latency?

 We cannnot check accurate latency of these AHB SINGLE bus accesses in chip.  So we suggest if block size is less than 512, please use SDMA. 

For SD card or eMMC applications, ADMA mode should not cause this issue because the block size is 512Bytes for SD card and eMMC applications. One block read takes more than 2.8us for eMMC4.5, more than 5.4us for SD3.0 card, and much more time for legacy eMMC and SD cards.

For SDIO2.0/SDIO3.0 cards, whose minimum block size can be 4Bytes, ADMA modes should not be used.