the 74LVC595A shift registers reads the incoming data with the rising clock edge. The serial data output is also clocked on the rising edge of the SHCP. Could there be a problem when cascading several 74LVC595A devices, due to propagation delay and hold time? I mean the cascaded register has a hold time of minimum 1.5ns at 3.3V, the data output could have a propagation delay of 1.5ns. This means the second register can see a changing input pin 1.5ns after the clock pulse, so layout effects of a few ps can make my device unfunctional by reading strange things.
Is there a good way to avoid problems like this? Why isn't a additional Q7S flip flop in the device, which latches the data out at the falling clock edge?