A GPIO is connected to a FPGA and the GPIO set to Output High when running.
When S/W reset, they would like to drive the GPIO Low in order to reset the FPGA.
However the GPIO wouldn't go Low when reset.
They pulldown the pad externally in 10K resistor and set Keeper enabled during reset to IOMUX setting done.
(Keeper is disabled on normal operation).
Their question is,
With internal Keeper enabled, how much current should I give in order to driver the pin low?
I don't understand the question well but I think internal Keeper load doesn't effect on the current to drive the pin.
However from AN5078 "Influence of Pin Setting.." document describes Keeper has Typ 130K load.
From i.MX25 datasheet, Iol is 2.0mA for slow mode and Standard Drive GPIO pins.
So in order to drive the pin Low, minimum 2.0mA can be input to i.MX25.
Regardless the load of external pullup/down resistors and FPGA loads, how much current they should give in order to drive the pin output low?