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overlapping of TLB 1 in P1010

Question asked by Manish Raturi on Jul 27, 2016
Latest reply on Jul 28, 2016 by ufedor

Hi Team,


We are using P1010 e500V2 processor I have following doubt:

I want to understand , if we open three TLB which has overlapped address , what all bad things can happen in a system, TLBs entry is shown below:


TLB_1_0 = Base Address 0xF0000000 , SIZE = 256 MB , Target Device = Parallel Flash(boot flash) , Attributes = cache inhibited , write through , executable , Guarded (though we have open the 256 MB window the base address of the boot flash is 0xFc000000)


TLB_1_1 = Base Address 0xF0000000, SIZE = 64 MB, Target Device = FPGA 1, Attributes = cache inhibited , write through , Guarded


TLB_1_2 = Base Address 0xF0200000, SIZE = 128 KB, Target Device = FPGA 2, Attributes = cache inhibited , write through , Guarded


In above TLB'S virtual Address =  Physical Address.


My purpose of asking this question is that we are seeing very weird behavior in the system, some time when we try to write to 0xF0200000 where we have mapped FPGA 2 that write goes to FPGA 1 which is mapped to 0xF0000000.


Can the above overlapping of TLBS can cause this problem..?