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How to overcome IMX-6x SPI Driver Fifo limitation of 64 bytes

Question asked by bhupendra pawar on Jul 26, 2016
Latest reply on Jul 27, 2016 by hari nalacheruvu

Imx6x spi driver has the limitations in DMA and PIO mode I checked with all available kernel versions,

it transfers in chunk of 64 bytes as per fifo length.

I can see on CRO if data length is more than 64 bytes than spi drivers transfer it in multiple chunks of 64 bytes. And consecutive 64 bytes adds delay of 80us @spi clock 8Mzh.

There is delay involved in isr to copying data in fifo and read data from fifo.


Is there any possibility to transfer 256 bytes without adding delay.

I have previous experience with Pandaboard where all 256 bytes of data goes continuously without seeing any delay after 64 bytes.

Thanks in advance for the expert comment.