I want to realize the following scenario:
A FPGA module connected via EMI has a few FIFOs ( 16 bit ) in output ( schema in attachment ). Each of them has its own address and queue with length = x. When the queue reaches size = y ( y < x ), an interrupt is raised and the data are copied into circular buffers in IMX memory. I want to realize it using SDMA module.
In this moment I can copy the data in incremental mode but I need to freeze source (FIFO) address and increment only destination.
Any help will be appreciated.
Thank you in advance,