We are evaluating the T1014 processor for a new product. I know that the external DDR3 memory supports ECC. However does the L1 and L2 cache used by the e5500 core have ECC or parity?
Data Cache has 1 parity bit/byte and 1 parity bit/tag.
Instruction cache has 1 parity bit/word and one parity bit/tag.
Configurable ECC or parity protection for data array and parity protection for tag array
Please refer to the e5500 Core Reference Manual for additional details:
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