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About CCM/clocking descriptions in IMX6SDLRM Rev. 2, 04/2015

Question asked by shige uratan on Jul 22, 2016
Latest reply on Aug 5, 2016 by shige uratan

I'm confused about CCM/clocking.

 

For example,

in the Clock Tree figure Fig 18-3,

the divider: CSCMR2[LDB_DI0_IPU_DIV] is set to 1/7 as default.

But description in the "18.6.9 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)",

ldb_di0_ipu_div has reset value 0 and it means "divie by 3.5"

Which is correct ?

 

Also CS2CDR[LDB_DI0_CLK_SEL] can select MMDC_CH0 in the Clock Tree figure.

But at "18.6.12 CCM SSI2 Clock Divider Register (CCM_CS2CDR)",

ther

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