I am currently working on a board that has a i.MX 6 processor, specifically MCIMX6QP6AVT1AA. It has 4 DDR3 chips interfacing with it in a dual clamshell arrangement with a planned bus speed of 1066Mhz. I have been reviewing chapter 3 of the hardware development guide (http://cache.nxp.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf?fsrch=1&sr=1&pageNum=1).
The question I have is, will I have to worry about any package signal delays when constraining this processor? In other words, are all of the DDR3 signals length matched, or will we have to enter in delays on a per pin basis and compensate for them in the external board routing?