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PWM stops toggling between modulus register changes

Question asked by Mark Donkers on Jul 20, 2016
Latest reply on Jul 6, 2017 by Mark Donkers

We have a product that uses the MC13237.


We are using TPM1 and TPM2 to generate an FSK modulated stream of 1s and 0s. TPM1 is responsible for the bit timing (when the frequency needs to change) and TPM2 generates an edge-aligned PWM output that shifts between two frequencies – each representing a 0 or 1, we’ll call FREQ_LO and FREQ_HI, respectively.


The baseband (demodulated) data is essentially a UART format with 1 start bit, 8 data bits, 1 parity bit and 1 stop bit. When there is no data  to be sent, the idle state is 1 (aka FREQ_HI). I don't think this is important, but I thought I would share anyway.


The majority of the time, the system operates as expected, but randomly, the TPM2 stops modulating one of the frequencies.


For example, if the bit pattern 0-1-0-1 was to be modulated, the TPM2 output would output

DC -> FREQ_HI -> DC -> FREQ_HI, where DC is either GND or VCC. I suspect the DC level is an artifact of the last output state before the frequency (modulus) was changed.


I have scope captures of when the FREQ_LO is at a DC level. Note: I am unsure of whether the issue happens for the FREQ_HI bit time in other situations.




To fix the issue, we have tried to turn it off and back on by disabling all interrupts, refreshing all the TPM registers and re-enabling the system. This does not seem to fix the issue.


In some situation, the issue has been seen to correct itself, although we cannot correlate when or why. In other system, the issue continues for weeks and never corrects.


The only course of action that always fixes it is power on reset.


NXP’s site has no errata sheets, but I have been told although I understand the MC13237 SoC implements a GT60 core ( Unfortunately I have not heard back yet regarding what mask should be referenced.


Does anyone have any suggestions of what might cause this issue?


Thanks in advance for any help.