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Toggling UART2 GPIOs

Question asked by pro-supportengineer Employee on Jul 19, 2016
Latest reply on Jul 19, 2016 by Pavel Chubakov

Need to toggle UART2 GPIOs on QorIQ LS1043ARDB SDK 2.0 and need to understand how and which GPIOs are accessible sysfs for UART2 after writing to the RCW.


To toggle the UART2 GPIOs we already know it is necessary to write to the RCW using the CW QCVS/PBL-RCW tool.  We also know the UART function is not exposed on these pins once they’re configured for GPIO. 


To select the GPIO on UART2 pins the RCW would have to be modified with RCW[UART_BASE]=100, is this correct? Or should it be RCW[UART_BASE] = 011.  We only want to use UART2 and not UART1.


The information I need is similar to what was needed on i.MX6:


Writing the RCW gives access to the GPIOs, but it doesn't indicate any driver changes needed, addresses and offsets for UART2, or which /sys/class/gpio/gpioxxx to toggle for UART2 based on the gpio subsystem. Below we show how we did this for the i.MX6.


The question is how do we figure out which /sys/class/gpio/gpioxxx to toggle for UART2 on the LS1043ARDB SDK 2.0?


What is the command needed to send a value to the GPIOs equivalent to "echo 1 > /sys/class/gpio/gpio177/value" for the GPIO pins on I.MX6?


On imx6 Nitrogen we did the following, which is equivalent to writing the RCW on QorIQ SDK 2.0 for the LS1043ARDB:




pinctrl_uart1: uart1grp {           
fsl,pins = <    

     MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA  0x1b0b1

     MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA  0x1b0b1




pinctrl_uart1: uart1grp {

fsl,pins = <

       MX6QDL_PAD_SD3_DAT6__GPIO6_IO18        0x1b0b1

       MX6QDL_PAD_SD3_DAT7__GPIO6_IO17        0x1b0b1       



This causes the Linux’s PINMUX subsystem to use GPIOs instead of the UART similar to writing to the RCW.  These macros are defined in kernel/arch/arm/boot/dts/imx6q-pinfunc.h where there are offset (to the base) and one of the alts per each pin.


After this update the serial driver for UART1 will work but without external pins. Instead of this the pins will be controlled by the GPIO subsystem and this is the information we need to know for the LS1043A SDK 2.0 (how does the mapping work):


5*32+17 = 177 (GPIO<X-1>+IO<Y>)

5*32+18 = 178


At this point thee GPIOs will be available via the kernel’s SYSFS interface (we need to determine the UART2 GPIOs accessible to the SYSFS for the LS1043A SDK 2.0, similar to the I.MX6 below):


echo 177 > /sys/class/gpio/export

echo 178 > /sys/class/gpio/export

echo out > / sys/class/gpio/gpio177/direction


the first session:

watch -n 1 cat /sys/class/gpio/gpio178/value

the second session:

echo 1 > /sys/class/gpio/gpio177/value

and then:

echo 0 > /sys/class/gpio/gpio177/value