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Some feedback to i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015

Question asked by Martin Maurer on Jul 15, 2016
Latest reply on Sep 6, 2016 by Martin Maurer


Hello,

 

[Info/pages updated from rev. 1 to rev. 3, 07/2015]

 

here some feedback to "i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015".

 

1) According to page 507 PLL5 seem to go from 650MHz to 1300MHz.

But page 796 list 630MHz as one and only frequency. Cut&Paste error from PLL4?

 

2) Is 132MHz as default frequency correct for IPU2_DI0_CLK_ROOT? All other IPUx_DIy_CLK_ROOT show 180MHz...

(Page 808)

 

3) Page 859 shows "Selector for ldb_di1 clock multiplexer" even for "11–9 ldb_di0_clk_sel".

 

4) Page 1625: "Input video Vertical active pixel region width. Number of Vertical active lines [0...4095]."

But field has only 8 bits, so max 255?

 

5) Page 2892: IPU_DP_COM_CONF_SYNC Register address 0x1F40000. Correct? Same for SRM entries

and all following entries up to following page and register IPU_DP_CSC_ASYNC1_1?

(to page 2893 and 2894)

 

6) Page 3251: Bit 18: "Post-Processing Task color conversion RGB-->YUV enable. This bit enables YUV-->RGB."

Must be "RGB-->YUV" at end of sentence?

 

Best regards,

 

Martin

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