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T1040RDB T1040D4RDB disambiguation

Question asked by Stefan Lange on Jul 11, 2016
Latest reply on Jul 11, 2016 by alexander.yakovlev

Hello NXP team,


I am a little unsure about the disambiguation of the T1040RDB and T1040D4RDB.


I have an RDB at my place.

The front panel sticker says "T1040RDB"

The PCB silkscreen print says "T1040RDB Ver. B"

Uboot bootlog is as seen below.

A sticker on the PCB says "SCH28215 Rev. B"


I persume it is the T1040D4RDB but would like to be sure.


Thanks and best regards,






UBoot Bootlog




U-Boot 2014.01QorIQ-SDK-T1040-BSP0.2 (Mar 07 2014 - 01:04:58)


CPU0:  T1040E, Version: 1.0, (0x85280010)

Core:  e5500, Version: 2.0, (0x80241020)

Clock Configuration:

       CPU0:1400 MHz, CPU1:1400 MHz, CPU2:1400 MHz, CPU3:1400 MHz,

       CCB:600  MHz,

       DDR:800  MHz (1600 MT/s data rate) (Asynchronous), IFC:150  MHz

       FMAN1: 600 MHz

       QMAN:  300 MHz

       PME:   300 MHz

L1:    D-cache 32 KiB enabled

       I-cache 32 KiB enabled

Reset Configuration Word (RCW):

       00000000: 0c18000e 0e000000 00000000 00000000

       00000010: 66000002 80000002 ec027000 01000000

       00000020: 00000000 00000000 00000000 00032810

       00000030: 00000000 0342500f 00000000 00000000

Board: T1040RDB

Board rev: 0x01 CPLD ver: 0x05, vBank: 0

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM 18KSF51272AZ-1G6K1

2 GiB left unmapped

    DDR: 4 GiB (DDR3, 64-bit, CL=11, ECC on)

       DDR Chip-Select Interleaving Mode: CS0+CS1

Flash: 256 MiB

L2:    256 KiB enabled

Corenet Platform Cache: 256 KiB enabled

Using SERDES1 Protocol: 102 (0x66)

NAND:  1024 MiB


PCIe1: Root Complex, no link, regs @ 0xfe240000

PCIe1: Bus 00 - 00

PCIe2: Root Complex, x1 gen1, regs @ 0xfe250000

  02:00.0     - 8086:10b9 - Network controller

PCIe2: Bus 01 - 02

PCIe3: Root Complex, no link, regs @ 0xfe260000

PCIe3: Bus 03 - 03

PCIe4: Root Complex, no link, regs @ 0xfe270000

PCIe4: Bus 04 - 04

In:    serial

Out:   serial

Err:   serial

Net:   Initializing Fman

Fman1: Uploading microcode version 106.4.14

FSL_MDIO0:0 is connected to FM1@DTSEC1.  Reconnecting to FM1@DTSEC2

FSL_MDIO0:0 is connected to FM1@DTSEC2.  Reconnecting to FM1@DTSEC3

e1000: 00:1b:21:33:5c:5d

       FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4 [PRIME], FM1@DTSEC5, e1000#0

Warning: e1000#0 MAC addresses don't match:

Address in SROM is         00:1b:21:33:5c:5d

Address in environment is  00:04:9f:03:05:e9