i.MX6SoloX Cortex-M4 cache memory and MPU

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i.MX6SoloX Cortex-M4 cache memory and MPU

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davidjaouen
Contributor III

Hi,

I'm trying to define memory regions using the MPU of the Cortex-M4 of the i.MX6SoloX. I'm using the i.MX6SX Sabre SD board.

I would like to define a region of 256MB of cached memory at 0x80000000 and another region of 256MB of uncached memory at 0x90000000. So, I configured the Cortex-M4 MPU to do so.

Then, I made 3 tests to check whether the cache is active or not on each memory region. The test is just a for() loop that does nothing except incrementing its index.

1st test:

I disabled data cache (LMEM IP) and measured its execution time (~ 11000ms).

2nd test:

I enabled the data cache (LMEM IP) and executed the code from the cached memory region (~610ms).

3rd test:

I enabled the data cache (LMEM IP) and executed the code from the uncached memory region (~970ms).

It appears that the execution time from 2nd and 3rd tests are almost the same where I expected to have an execution time for the 3rd test almost the same as for the 1st test.

So, even when a memory region is configured to be uncached in the MPU, the data cache is active.

Does the LMEM IP take care of the memory regions cache policies configured in the Cortex-M4 MPU?

And how can I configure the i.MX6SX to disable cache for memory regions configured to be uncached?

Best regards,

David

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Yuri
NXP Employee
NXP Employee

Hello,

  Please refer to the recent RTOS patch regarding cache setting.

[6Solox/Freertos]The Patch to fix the LMEM Address for FreeRTOS_BSP_1.0.0_iMX6SX to enable M4 Cache ... 

Have a great day,
Yuri

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davidjaouen
Contributor III

Hi Yuri,

Thanks for your answer but my problem is not to be able to enable or disable the cache (I'm already using 0xE0082000 base address for LMEM).

I want to use the cortex-M4 MPU to configure cache policies of memory regions but it seems LMEM does not take care of the MPU configuration (cache is enabled when accessing memory region configured to be uncached in the MPU).

Is there any way to configure the cache to be active for some memory regions and inactive for others?

Best regards,

David

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Yuri
NXP Employee
NXP Employee

Hello,

You are right - " LMEM does not take care of the MPU configuration".

Regards,

Yuri.

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