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I am bringing up our T2081 design. WE need to use two PCIe ports x4 and we have selected SRDS_PR TCL_S1 =0xAA

Question asked by Joel Bovier on Jul 7, 2016
Latest reply on Jul 12, 2016 by Joel Bovier

When the T2081 fetch its RCW, SerDes1 PLL 1 is not locking because we supply 100MHz on

SD1_CLK1 and SD1_CLK2.  (HRST_REQn asserted after RCW read from NOR Flash)

- We need PCIe4_x4  Gen3 and PCIe3_x4 Gen2.

Do you have a workaround to operate with SD1_CLK1 and SD1_CLK2 at 100MHz ?

I can live with PCIe4_x4  Gen2 (in place of Gen3)


NOTA : In our design we are not able to supply 155MHz on SD1_CLK1