Where do I access inbound MSI interrupts to the T1040 processor?

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Where do I access inbound MSI interrupts to the T1040 processor?

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andrewostler
Contributor I

The target address for the MSI window is CCSR, but i'm assuming it doesn't write over the config registers at 0xFE000000.  Where does this MSI data get written?

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ufedor
NXP Employee
NXP Employee

The MSI data has to be written to the MSIIR register in the PIC.

Please refer to the QorIQ T1040 Reference Manual, 28.12.2.2.2 MSI handling.

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andrewostler
Contributor I

It looks like this writes a single bit inside of the register you choose to forward it to. Is this correct or does the MSI contain data that can be read somewhere?

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ufedor
NXP Employee
NXP Employee

MSI is an interrupt which is signalled by setting specified bit in a specified register - see description of the MSIIRA(B,C) in the QorIQ T1040 Reference Manual.

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andrewostler
Contributor I

Thank you for your help.  It seems that I'm unable to write to the msi message control register in order to enable MSIs in my 1040 which is set up at the Root.  Any idea why this would be the case?  I am also reading 0s in the MSI message capability id register which it says is supposed to be 0x05.

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ufedor
NXP Employee
NXP Employee

Please explain how did you read the registers and provide corresponding logs if you've used U-Boot to do that.

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andrewostler
Contributor I

I am reading this register by writing to the PEX_CONFIG_ADDR register:   0x80000088.  Then i read the PCIE_CONFIG_DATA register.

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ufedor
NXP Employee
NXP Employee

> PEX_CONFIG_ADDR register

> PCIE_CONFIG_DATA register

What are addresses of the registers?

Which RCW you're using?

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andrewostler
Contributor I

sorry I mistyped that second register, it is the PEX_CONFIG_DATA register.   The ADDR register is: 0xFE250000      DATA is:  0xFE250004.  The offsest of 0x250000 is because we are using the PEX2 controller.  I'm not sure what the RCW is that you are referring to, it you could please explain.

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ufedor
NXP Employee
NXP Employee

> I'm not sure what the RCW is that you are referring to, it you could please explain.

Please refer to the QorIQ T1040 Reference Manual, 4.6.5 Reset configuration word (RCW)

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andrewostler
Contributor I

The RCW status register reads:

0x00:     0x0810000C     0x08000000     0x00000000     0x00000000

0x08:     0x66000002     0x80008002     0x5C027000     0x21002400

0x10:     0x00000000     0x00000000     0x00000000     0x00030810

0x18:     0x00000000     0x8156500F     0x00000000     0x00000000

Is this what you are looking for?

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ufedor
NXP Employee
NXP Employee

What is the SD1_REF_CLK1 frequency?

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andrewostler
Contributor I

I'm not sure where i would find this.

Edit:  in the RCW data it looks like this is set to 125 MHz.

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ufedor
NXP Employee
NXP Employee

Which board is used?

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andrewostler
Contributor I

T1040

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ufedor
NXP Employee
NXP Employee

Does your answer mean that the board is a proprietary one?

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andrewostler
Contributor I

I'm not sure what further detail you are asking about the board.  The T1040 RDB board has it's specs on the NXP website.  Sorry if I'm not understanding your question.

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ufedor
NXP Employee
NXP Employee

Excuse me, but your response was "T1040" only - how could I guess that you've meant T1040RDB?

You wrote:

> The ADDR register is: 0xFE250000

Please try 0xFFE250000

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andrewostler
Contributor I

I apologize for not being specific, i didn't realize there were different versions of that board.

The problem is not with accessing the config registers.  I'm able to access other config registers at 0xFE250000, but this specific one is inaccessible.

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ufedor
NXP Employee
NXP Employee

> I am reading this register by writing to the PEX_CONFIG_ADDR register:   0x80000088.

Please note that in the provided RCW the HOST_AGT_PEX field is 000 (All PEXn in RC mode).

Also please refer to the QorIQ T1040 Reference Manual, 28.10 PCI compatible device-specific configuration space, Figure 28-5. PCI Compatible Device-Specific Configuration Space, byte 0x4D "Next Pointer (EP: 0x88/RC: NULL)" - this means that MSI capabilities are specified only for EPs.

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andrewostler
Contributor I

ok, that's what I needed to know.  I guess I'm just not sure what other things i need to configure on the RC side.  I am setting the IWBAR  and IWBEAR to the same address which our device is sending it's MSIs to.  I also set the PEXMSIIWAR to 0x80E00000.  Is there any additional configuration necessary?

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