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i.MX6 BT.1120 input

Question asked by Pierre-Olivier Huard on Jul 5, 2016
Latest reply on Jul 7, 2016 by Pierre-Olivier Huard


We are currently working on BT.1120  input of the CSI, but we have some issues.

The video comes from a FPGA, 8bits for Y, 8bits for CbCr, total 16bits, one clock : Pixclk.

The SAV and EAV  are embedded, progressive mode, single data rate.


We connected C0~C7 to IPU1_CSI1_DATA2~9 and Y0~Y7 to IPU1_CSI1_DATA12~19.

In the device tree, all this pins are set to 0xb0b1, the VSYNC, HSYNC,DATA0,1,10,11 are set to PAD_CTRL_HYS_PD


We created a driver, and communicate to V4l2 driver .

This is our configuration :


pixelformat : V4L2_PIX_FMT_YUYV

bt_sync_correct = 0

nobt_vs_inv = 0

nobt_hs_inv = 0


We dumped some registers :

CSI_SENS_CONF = 0x00000A50

CSI_ACT_FRM_SIZE = 0x0437077F (1920x1080)

CSI_CCIR_CODE_3 = 0x00FF0000


When we launch the driver, we have the following error :

    ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0


Is the configuration correct? We found a lot of different patches (sii9135,tvin), and we used it as templates.

Is there any debugging tool for v4l2? A log could be helpful.


Pierre-Olivier Huard