hi All
i am using imx6dual and 3.10.17 kernel
i would like to know about VPU
how to know the current frequency of VPU ? and how to increase and what is maximum supported?
Hi,
Maximum supported trhoughput, is 72,576,000 pixels /s @ VPU frequency of 266 mhz
2 x 1024 x 600 x 60hz = 73,728,000
And you can refer to VPU max frequency in our community.
Have a great day,
Dan
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why did you multiply the result with 2 in the beginning?
2 x 1024 x 600 x 60
Hi, NXP
I am using IMX6 dual module with the vpu firmware file "vpu_fw_imx6q.bin (md5 af2a9be3c6cf797afd8e8bf7a8c4a654)"
and able to encode
but I am experiencing a strange behavior while streaming the encoded h264 data through RTPH264PAY plugin and decoding with VLC (2.2.4)
at every 35 to 45 mins, the decoder (vlc-media-player) displays warning "can not decode one frame" , do you have any idea about this ?
i tried to use firmware vpu_fw_imx6d.bin (d4a0fc04c9d7f5f5b114fb8c60566f53) which is not working throwing version mismatch error.
is vpu firmware is correct ? if yes, why there are two firmware with files ? even though my module is dual, it is working with vpu_fw_imx6q.bin but not with vpu_fw_imx6d.bin, what is the difference between them ?
hi Dan
thanks for reply.
i am using imx6 dual, for HD and SD video encoding and streaming,
i found some frame losses with dual stream, i would like to increase vpu freq to 325Mhz and test.
i did not get clear picture how to increase clock to 325MHZ
i am using 3.10.17 kernel
please let me know how to increase vpu to 325mhz
regards
nagendra
Hi All
i am using following patch (3.10.17) to increase my VPU frequency to 352Mhz
and my vddsoc and vddpu showing
vddpu: 725 <--> 1450 mV at 1150 mV
vddsoc: 725 <--> 1450 mV at 1200 mV
please let me know how to increase these voltages to 1250 mv (required for VPU) ?
patch used to increase vpu freq.
753 #ifdef CONFIG_MX6_VPU_352M
754 /*
755 * If VPU 352M is enabled, then PLL2_PDF2 need to be
756 * set to 352M, cpufreq will be disabled as VDDSOC/PU
757 * need to be at highest voltage, scaling cpu freq is
758 * not saving any power, and busfreq will be also disabled
759 * as the PLL2_PFD2 is not at default freq, in a word,
760 * all modules that sourceing clk from PLL2_PFD2 will
761 * be impacted.
762 */
763 imx_clk_set_rate(clk[pll2_pfd2_396m], 352000000);
764 imx_clk_set_parent(clk[vpu_axi_sel], clk[pll2_pfd2_396m]);
765 pr_info("VPU 352M is enabled!\n");
766 #endif
regards
nagendra