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MPC8377: PCIe inbound addressing more restrictive than PCI32 ?

Question asked by Sylvain Bourré on Jun 30, 2016
Latest reply on Jul 12, 2016 by Serguei Podiatchev



We developed several designs based on MPC8377VRAGD with 2-GByte SDRAM,  connected to an FPGA through PCI32 (the FPGA has no local SDRAM attached).

The FPGA fills up the SDRAM attached to the MPC with acquisition data (1768MB of data from physical addr.  0x1000_0000). Everything works fine.


We decided to move from PCI32 to PCIe for a new design (MPC8377 is RC).

The FPGA,  PCIe initiator, is not able to fill up the whole SDRAM with data: posted TLP writes silently fail when destination addr is >= 0x3FFF_F000. TLP reads from the same memory locations fail with completion errors.


I started to investigate in low level u-boot init code and MPC8379ERM and discovered the following:

-    PCI inbound window attributes registers (PIWARn) allow to specify up to 2-Gbyte window size

-    PCI Express RC inbound window attributes registers (PEX_RCIWAR0 –PEX_RCIWAR3) allow to specify up to 256-Mbyte window size


So I have the feeling that our FPGA won’t be able write more than 1GB (4x256MB) into the MPC’s SDRAM.

Can you, please, confirm or infirm this?


If so, any idea for a workaround (dynamic RCIWAR reconfiguration for instance) ?


Thank you in advance for any comment/advice.