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Question, i.MX6S DPMI timing

Question asked by AVNET JAPAN FAE (team share account) on Jun 29, 2016
Latest reply on Jul 28, 2016 by Yuri Muhin

Dear team,


I would like to ask about GMPI timing of i.MX6Solo.

In i.MX6Solo datasheet(IMX6SDLIEC, Rev.5), NF16((DS × T -0.67)/18.38) is depicted in Figure 32.

Can I understand that an external NAND chip should set Data within (DS × T -0.67)/18.38 nSec after the falling edge of NAND_RE_B?

My customer believes that setup time should be specified the time before the rising edge of NAND_RE_B written as red line in below.