P5020 PIR Values out of Reset

[stefanschmitt]

I am looking for the P5020 PIR Values out of Reset. Where are those described? For the T4240, the corresponding information is included in the RM (Table 7-4. PIR Values out of Reset). However, the P5020 RM does not include such details.

[Pavel · Accepted solution]

1. 1. The core register PIR is a processor ID register. Out of reset, core 0 is guaranteed to have PIR of 0. Cores 1-7 are guaranteed to only have a non-zero PIR (not the respective core number such as 1,2,3 etc). Software should initialize the PIR for cores 1 thru 7 to desired values (usually 1,2,3 etc) by reading the WHOAMI register from MPIC. The MPIC's PIR register is completely different from this. It is a register that software can write to to hard reset individual cores.
2. 2. WHOAMI register is located in the MPIC block in the platform. When each core reads this register it is guaranteed to return the respective core number (i.e. core 1 returns 1, core 2 returns 2 etc). Software may always read this register to determine the core number or may initialize the core PIR's and use those.

Have a great day,
Pavel Chubakov

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------