I am attempting to talk to an FPGA via GPCM on the P1013's local bus. The FPGA is a 16-bit device with 24-bit addressing. What I see on the logic analyzer is that the FPGA receives the data intact, but with the addressing mangled.
I've configured BR1 / ORg1 for a base address of 0xEFF00000 and a size of 64KB, and enabled LAWBAR/LAWAR for those values. The FPGA is expecting data at a base address (from it's perspective) of 0x5800.
So if I do
volatile unsigned short *ptr = (volatile unsigned short *)(0xEFF00000 + 0x5800);
*ptr = 0xAAAA;
What address will actually be put on the local bus? Only address lines 0..23 are connected, so is the high byte just discarded? If so, that would be an effective address 0x00F05800. Is it the offset from the BR1 base address that is put on the bus? If so, that would give me the effective address of 0x5800 that I want but am not seeing.
So... how do I arrange the addressing on the 32-bit P1013 such that the 24-bit addressed FPGA will see only the low 16-bits?