I have a KL26 whose core clock is set-up at 48MHz. I have set-up a SPI-DMA transfer similar to the example of KSDK 1.3.0. The data transfer is started by an external signal on a GPIO (PTC9) signal edge (interrupt). It works! I have measured on an oscilloscope a delay of approx. 10 microseconds between the edge of the GPIO signal and the start of the SPI transfer …
The interrupt function is very simple (for test purpose) …
DMA_DCR1|=0x40000000u; //start DMA1 transfer
DMA_DCR0|=0x40000000u; //start DMA0 transfer
In the main program loop, I use polling to set-up the spi BCR bits again and clear the done bit after each transfer.
My question is: can it be faster? If yes, how can I make the delay between signal edge and the start of SPI-DMA transfer shorter? How short?
I read somewhere about 10-12 clock cycles (for interrupt alone) … that would be approx. 0.2 microsecond right. So where do the 10 microseconds come from?
Thank you for you inputs.