I have a question about S12Z MagniV(e.g.S12ZVM).
About interrupt, where I-bit mask/unmask feature is implemented?
On S12Z CPU? Or INT module?
I cannot find I-bit signal path on device RM and S12Z core manual.
The I-bit is a part of CPU register CCR. The value of bit is connected to an interrupt module S12ZINTV0.
The picture is similar to previous MCUs, Figure 1-1 in http://www.nxp.com/files/microcontrollers/doc/ref_manual/S12INTV1.pdf
From your commnent, I imagine the following signal path/connection.
My understanding summary:1. SEI/CLI instructions act for CCR I-bit2. I-bit set/clear status signal is connected to INT modules3. I-bit set/clear status signal and each peripheral interrupt signal are muxed in INT modules INT module judges Interrupt release or pending based on these signals and register settings
(e.g. PRIOLVL[2:0] in S12Z INT module)4. Output signals are connected to CPU
Is my understanding correct?If not, could you point out the wrong point/description?
First of all I am sorry for delay because of vacation.
If I have not missed anything then your description is OK.
I have also asked Radek for double check.
BTW; I really do not understand why you need such an info. From user point of view it is enough to see it as a black box and just understand interrupt selection, nesting possibilities and setup.
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