AnsweredAssumed Answered

i.MX6 SoloX Cortex A9 and M4 data transfer bandwidth

Question asked by Marc S on Jun 27, 2016
Latest reply on Jan 12, 2017 by ALLEN BLAYLOCK

We are looking to use an i.MX6 SoloX for a low power data acquisition/processing platform (instead of using a Xilinx Zynq SoC) and I can't find an answer to this question on the data transfer bandwidth between the ARM Cortex A9 and M4. I understand that data is transferred between the two cores through shared memory through RPMsg to ensure no hardware conflicts. I also looked through the code examples for the ping pong and character string transfers.  Does any one know what kind of bandwidths can be transferred between the two cores?  In this data acquisition application, the plan was to use the M4 to acquire data through eCSPI at 25 Mbps and transfer that data to the A9 for processing and storage.  Surely, using shared memory that kind of memory bandwidth can be supported, but can the shared memory APIs handle that?  Thank you for any info on this topic.

Outcomes