The I2C1 peripheral is clocked by CLK_APB3_I2C1. I initially had APB3_CLK, which is the base clock of CLK_APB3_I2C1, set to take as input PLL1, which is running at 204 MHz. Therefore I2C1 was clocked at 204 MHz.
When clocked at 204 MHz, the I2C1 peripheral runs for about a minute and then starts to fail. It either will not generate any more interrupts or it will generate continuous interrupts with state=0, which indicates an I2C bus error.
If I change APB3_CLK to run from IDIVA, which is set to divide PLL1 by 2, I2C1 runs fine. I checked the errata and there's no mention of I2C1 having issues at 204 MHz. The 4358 UM (UM10503) explicitly states:
Clock to the I2C1 register interface and I2C1 peripheral clock: BASE_APB3_CLK CLK_APB3_I2C1 up to 204 MHz
Anyone know why I2C1 won't run at 204 MHz?