If you search this forum (to see if anyone else had had a similar problem in previous years) you'll find:
MCF547x FlexBus Timing
That is a question about FlexBus timing in an MCF547x chip. It mentions your missing SWSEN, BEM, BSTR and BSTW bits If you look in the Data Sheet for that chip you'll find that these are Burst Enable, Burst Read and Write and Secondary Wait States Enable. The "SWS" field is also missing.
The MCF547x has Burst Mode on its Flex Bus. The MCF51MM and MCF51JE (this manual has the same fault) doesn't have Burst Mode on its Mini Flex Bus, but "Table 4-5. Mini-FlexBus Register Summary" lists those bits.
This is a cut-and-paste error from another manual, or a copy from some generic documentation for that module that is implemented with Burst Mode in the MCF54 chips, but doesn't have it on the MCF51 chips.
That has nothing to do with your problem.
Could you please describe your problem better? Get it translated better for a start. Include some Oscilloscope Traces as well if you can.
MFBPC1=0x03; AD0, AD1 are enabled, AD2-AD7 DISABLED
MFBPC2=0x00; AD8-AD15 DISABLED
MFBPC3=0xF0; D0-D3 enabled
MFBPC4=0xDF; CS0, CD1, RW, D0-D7 enabled, OE disabled
MBCSCR0=0x003FFD40; Max hold and delay, max wait state, auto ack, 8 bit
MBCSAR0=0x00400000; Address
MBCSMR0=0x00000001; Valid
MBCSCR1=0x003FFD40; Same as above
MBCSAR1=0x00500000; Address
MBCSMR1=0x00000001; Valid
All looks OK (if very slow, with 63 wait states per cycle. That might explain "always asserted and only off for a short period". That may be what you've programmed and what your code is doing if it is continuously accessing 0x005xxxxx.
Looking at your setup and the Reference Manual, you have Chip Select delayed by 4 clocks (more than is the default for CS1) and 3 clocks of Address Hold. Back to back cycles look to have CS deasserted for 3 clocks, so you should be seeing CS high for 10 clocks (410ns) and then low for 64 clocks (2666ns).
If you are looking at a signal that is only going high for ONE 24MHz clock cycle, are you sure you're not looking at FB_ALE? It would be high for 1 clock or 41ns and then low for 74 clocks or 3.1us minimum.
Tom
